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Features
* Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store * * * * * * * * * * * *
Configuration Programs for Field Programmable Gate Arrays (FPGAs) 3.3V Output Capability 5V Tolerant I/O Pins In-System Programmable (ISP) via 2-wire Bus Simple Interface to SRAM FPGAs Compatible with Atmel AT40K and AT94K Devices, Altera FLEX(R), APEXTM Devices, Lucent ORCA(R) FPGAs, Xilinx XC3000TM, XC4000TM, XC5200TM, Spartan(R), Virtex(R) FPGAs, Motorola MPA1000 FPGAs Cascadable Read-back to Support Additional Configurations or Higher-density Arrays Low-power CMOS FLASH Process Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC Packages), 20-lead PLCC, 44-lead PLCC and 44-lead TQFP Packages Emulation of Atmel's AT24CXXX Serial EEPROMs Low-power Standby Mode Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System Reconfiguration Fast Serial Download Speeds up to 33 MHz
In-System Programmable Configuration PROM AT17F040 AT17F080
Description
The AT17F Series of In-System Programmable Configuration PROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17F Series device is packaged in the 8-lead LAP, 20-lead PLCC, 44-lead PLCC and 44-lead TQFP, see Table 1. The AT17F Series Configurator uses a simple serial-access procedure to configure one or more FPGA devices. The AT17F Series Configurators can be programmed with industry-standard programmers, Atmel's ATDH2200E Programming Kit or Atmel's ATDH2225 ISP Cable. Table 1. AT17F Series Packages
Package 8-lead LAP 20-lead PLCC 44-lead PLCC 44-lead TQFP AT17F040 Yes Yes - - AT17F080 Yes Yes Yes Yes
Advance Information
Rev. 3039B-CNFG-10/02
1
Pin Configuration
8-lead LAP
DATA CLK RESET/OE CE
1 2 3 4
8 7 6 5
VCC SER_EN CEO (A2) GND
20-lead PLCC
3 2 1 20 19 NC GND PAGESEL0 NC NC 9 10 11 12 13
NC DATA NC VCC NC CLK NC RESET/OE PAGESEL1 CE 4 5 6 7 8 18 17 16 15 14 NC SER_EN PAGE_EN READY CEO (A2)
2
AT17F040/080
3039B-CNFG-10/02
3039B-CNFG-10/02
NC NC NC NC NC NC NC NC NC NC NC
NC NC NC NC NC NC NC NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11
7 8 9 10 11 12 13 14 15 16 17
NC RESET/OE PAGESEL0 CE NC NC GND PAGESEL1 NC CEO(A2) NC
12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34
NC CLK NC NC DATA PAGE_EN VCC NC NC SER_EN NC
NC RESET/OE PAGESEL0 CE NC NC GND PAGESEL1 NC CEO/A2 NC
18 19 20 21 22 23 24 25 26 27 28
6 5 4 3 2 1 44 43 42 41 40
NC CLK NC NC DATA PAGE_EN VCC NC NC SER_EN NC
44 PLCC
44 TQFP
39 38 37 36 35 34 33 32 31 30 29
33 32 31 30 29 28 27 26 25 24 23 NC NC NC NC NC NC NC NC NC NC READY
NC NC NC NC NC NC NC NC NC NC READY
AT17F040/080
3
Block Diagram
READY
Power-on Reset
Reset
Clock/Oscillator Logic
CLK
PAGE_EN PAGESEL0 PAGESEL1
Config. Page Select
CEO(A2) Serial Download Logic
2-wire Serial Programming
DATA
Flash Memory
CE/WE/OE Data Address
CE Control Logic RESET/OE SER_EN
Device Description
The control signals for the configuration memory device (CE, RESET/OE and CLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration device without requiring an external intelligent controller. The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven Low, the configuration device resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17F Series Configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE. When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset.
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AT17F040/080
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AT17F040/080
Pin Description
AT17F040 Name DATA CLK PAGE_EN PAGESEL0 PAGESEL1 RESET/OE CE GND CEO A2 READY SER_EN VCC I/O I/O I I I I I I - O 6 I O I - - 7 8 15 17 20 - 7 8 15 17 20 29 41 44 23 35 38 14 6 14 27 21 8 LAP 1 2 - - - 3 4 5 20 PLCC 2 4 16 11 7 6 8 10 8 LAP 1 2 - - - 3 4 5 AT17F080 20 PLCC 2 4 16 5 7 6 8 10 44 PLCC 2 5 1 20 25 19 21 24 44 TQFP 40 43 39 14 19 13 15 18
DATA CLK PAGE_EN
Three-state DATA output for configuration. Open-collector bi-directional pin for programming. Clock input. Used to increment the internal address and bit counter for reading and programming. Input used to enable page download mode. When PAGE_EN is high the configuration download address space is partitioned into 4 equal pages. This gives users the ability to easily store and retrieve multiple configuration bitstreams from a single configuration device. This input works in conjunction with the PAGESEL inputs. PAGE_EN must be held low if paging is not desired. When SER_EN is Low (ISP mode) this pin has no effect. Page select inputs. Used to determine which of the 4 memory pages are targeted during a serial configuration download. The address space for each of the pages is shown in Table 2. When SER_EN is Low (ISP mode) these pins have no effect. Table 2. Address Space
Paging Decodes PAGESEL = 00, PAGE_EN = 1 PAGESEL = 01, PAGE_EN = 1 PAGESEL = 10, PAGE_EN = 1 PAGESEL = 11, PAGE_EN = 1 PAGESEL = XX, PAGE_EN = 0 AT17F040 (4 Mbits) 00000 - 0FFFFh 10000 - 1FFFFh 20000 - 2FFFFh 30000 - 3FFFFh 00000 - 3FFFFh AT17F080 (8 Mbits) 00000 - 1FFFFh 20000 - 3FFFFh 40000 - 5FFFFh 60000 - 7FFFFh 00000 - 7FFFFh
PAGESEL[1:0]
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3039B-CNFG-10/02
RESET/OE
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver. Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low). Ground pin. A 0.2 F decoupling capacitor between VCC and GND is recommended. Chip Enable Output (active Low). This output goes Low when the address counter has reached its maximum value. If the PAGE_EN input is set High, the maximum value is the highest address in the selected partition. The PAGESEL[1:0] inputs are used to make the 4 partition selections. If the PAGE_EN input is set Low, the device is not partitioned and the address maxvalue is the highest address in the device, see Table 2 on page 5. In a daisy chain of AT17F Series devices, the CEO pin of one device must be connected to the CE input of the next device in the chain. It will stay Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay High until the entire EEPROM is read again. Device selection input, A2. This is used to enable (or select) the device during programming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor. Open collector reset state indicator. Driven Low during power-up reset, released when power-up is complete. (recommended 4.7 k pull-up on this pin if used). Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low enables the 2-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC. +3.3V (10%).
CE
GND CEO
A2 READY SER_EN
VCC
6
AT17F040/080
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AT17F040/080
FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory. The AT17F Serial Configuration PROM has been designed for compatibility with the Master Serial mode. This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xilinx applications.
Control of Configuration
Most connections between the FPGA device and the AT17F Serial Configurator PROM are simple and self-explanatory. * * * * * The DATA output of the AT17F Series Configurator drives DIN of the FPGA devices. The master FPGA CCLK output drives the CLK input of the AT17F Series Configurator. The CEO output of any AT17F Series Configurator drives the CE input of the next Configurator in a cascade chain of configurator devices. SER_EN must be connected to VCC (except during ISP). The READY pin is available as an open-collector indicator of the device's reset status; it is driven Low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. PAGE_EN must be held Low if download paging is not desired. The PAGESEL[1:0] inputs must be tied off High or Low. If paging is desired, PAGE_EN must be High and the PAGESEL pins must be set to High or Low such that the desired page is selected, see Table 2 on page 5.
*
Cascading Serial Configuration Devices
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded configurators provide additional memory. After the last bit from the first configurator is read, the clock signal to the configurator asserts its CEO output Low and disables its DATA line driver. The second configurator recognizes the Low level on its CE input and enables its DATA output. After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE on each configurator is driven to its active (Low) level. If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive (High) level.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. The AT17F parts are read/write at 3.3V nominal. Refer to the AT17F Configuration application note available on the Atmel web site (www.atmel.com) for more programming details. The AT17F Series Configurators enter a low-power standby mode whenever CE is asserted High. In this mode, the AT17F Configurator consumes less than 50 A of current at 3.3V. The output remains in a high-impedance state regardless of the state of the OE input.
Standby Mode
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3039B-CNFG-10/02
Absolute Maximum Ratings*
Operating Temperature...................................... -4C to +85 C Storage Temperature ..................................... -65 C to +150C Voltage on Any Pin with Respect to Ground ..............................-0.1V to VCC +0.5V Supply Voltage (VCC ) .........................................-0.5V to +4.0V Maximum Soldering Temp. (10 sec. @ 1/16 in.)............. 260C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
Operating Conditions
AT17F Series Configurator Symbol Description Commercial VCC Industrial Supply voltage relative to GND -0C to +70C Supply voltage relative to GND -40C to +85C Min 2.97 2.97 Max 3.63 3.63 Units V V
DC Characteristics
AT17F040 Symbol VIH VIL VOH VOL VOH VOL ICCA IL ICCS Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage (IOH = -2.5 mA) Low-level Output Voltage (IOL = +3 mA) High-level Output Voltage (IOH = -2 mA) Low-level Output Voltage (IOL = +3 mA) Supply Current, Active Mode Input or Output Leakage Current (VIN = VCC or GND) Commercial Supply Current, Standby Mode Industrial 100 200 A -10 2.4 Industrial 0.4 5 10 100 -10 0.4 5 10 200 V mA A A Commercial 0.4 2.4 0.4 V V Min 2.0 0 2.4 Max VCC 0.8 AT17F080 Min 2.0 0 2.4 Max VCC 0.8 Units V V V
8
AT17F040/080
3039B-CNFG-10/02
AT17F040/080
AC Characteristics
CE TSCE RESET/OE TLC CLK TOE TCE DATA TOH TCAC TOH TDF THC THOE TSCE THCE
AC Characteristics when Cascading
RESET/OE
CE
CLK TCDF DATA
LAST BIT FIRST BIT
TOCK CEO
TOCE
TOOE
TOCE
9
3039B-CNFG-10/02
AC Characteristics
AT17F040 Symbol TOE(1) Description Commercial OE to Data Delay Industrial Commercial CE to Data Delay Industrial Commercial CLK to Data Delay Industrial Commercial TOH Data Hold from CE, OE, or CLK Industrial Commercial CE or OE to Data Float Delay Industrial Commercial TLC CLK Low Time Industrial Commercial THC CLK High Time Industrial CE Setup Time to CLK (to guarantee proper counting) CE Hold Time from CLK (to guarantee proper counting) OE High Time (guarantees counter is reset) Maximum Input Clock Frequency SEREN = 0 Maximum Input Clock Frequency SEREN = 1 Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial 20 35 40 0 0 20 20 10 10 33 33 20 20 25 0 0 20 20 10 10 33 33 ns ns ns ns ns ns ns MHz MHz MHz MHz 20 20 20 20 ns ns 20 55 20 50 ns ns 0 55 0 50 ns ns 0 80 0 60 ns ns 60 75 60 55 ns ns 55 60 55 55 ns ns Min Max 50 AT17F080 Min Max 50 Units ns
TCE(1)
TCAC(1)
TDF(2)
TSCE
THCE
THOE
FMAX
FMAX Notes:
1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
10
AT17F040/080
3039B-CNFG-10/02
AT17F040/080
AC Characteristics When Cascading
AT17F040 Symbol TCDF (2) Description Commercial CLK to Data Float Delay Industrial Commercial CLK to CEO Delay Industrial Commercial CE to CEO Delay Industrial Commercial RESET/OE to CEO Delay Industrial Commercial FMAX Notes: Maximum Input Clock Frequency Industrial 33 33 MHz 1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels. 45 33 35 33 ns MHz 60 40 40 35 ns ns 60 55 55 35 ns ns 60 55 50 50 ns ns Min Max 60 AT17F080 Min Max 50 Units ns
TOCK(1)
TOCE(1)
TOOE(1)
11
3039B-CNFG-10/02
Thermal Resistance Coefficients(1)
Package Type 8CN4 Leadless Array Package (LAP) JC [C/W] JA [C/W](2) JC [C/W] JA [C/W] JA [C/W] JA [C/W]
(2)
AT17F040
AT17F080 - - - -
20J
Plastic Leaded Chip Carrier (PLCC)
44A
Thin Plastic Quad Flat Package (TQFP)
JC [C/W]
(2)
- - - -
17 62 15 50
44J
Plastic Leaded Chip Carrier (PLCC)
JC [C/W]
(2)
Notes:
1. For more information refer to the "Thermal Characteristics of Atmel's Packages", available on the Atmel web site, at http://www.atmel.com/atmel/acrobat/doc0636.pdf. 2. Airflow = 0 ft/min.
12
AT17F040/080
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AT17F040/080
Ordering Information
Memory Size 4-Mbit Ordering Code AT17F040-30TQC AT17F040-30BJC AT17F040-30TQI AT17F040-30BJI 8-Mbit AT17F080-30CC AT17F080-30JC AT17F080-30TQC AT17F080-30BJC AT17F080-30CI AT17F080-30JI AT17F080-30TQI AT17F080-30BJI Package 8CN4 - 8 LAP 20J - 20 PLCC 8CN4 - 8 LAP 20J - 20 PLCC 8CN4 - 8 LAP 20J - 20 PLCC 44A - 44 TQFP 44J - 44 PLCC 8CN4 - 8 LAP 20J - 20 PLCC 44A - 44 TQFP 44J - 44 PLCC Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C)
Industrial (-40C to 85C)
Package Type 8CN4 20J 44A 44J 8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) - Pin-compatible with 8-lead SOIC/VOID Packages 20-lead, Plastic J-leaded Chip Carrier (PLCC) 44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP) 44-lead, Plastic J-leaded Chip Carrier (PLCC)
13
3039B-CNFG-10/02
Packaging Information
8CN4 - LAP
Marked Pin1 Indentifier
E
D
A A1
Top View
0.10 mm TYP
Side View
L1
Pin1 Corner
8
1
e
7 2
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.94 0.30 0.45 5.89 4.89 NOM 1.04 0.34 0.50 5.99 5.99 1.27 BSC 1.10 REF 0.95 1.25 1.00 1.30 1.05 1.35 1 1 MAX 1.14 0.38 0.55 6.09 6.09 1 NOTE
6
3
A
b
5 4
A1 b D E
e1
L
e e1 L L1
Bottom View
Note: 1. Metal Pad Dimensions.
11/14/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP) DRAWING NO. 8CN4 REV. A
R
14
AT17F040/080
3039B-CNFG-10/02
AT17F040/080
20J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45
0.318(0.0125) 0.191(0.0075)
e E1 B E B1 D2/E2
D1 D A
A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 9.779 8.890 9.779 8.890 7.366 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 10.033 9.042 10.033 9.042 8.382 0.813 0.533 Note 2 Note 2 NOTE
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 20J REV. B
R
15
3039B-CNFG-10/02
44A - TQFP
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 11.75 9.90 11.75 9.90 0.30 0.09 0.45 NOM - - 1.00 12.00 10.00 12.00 10.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 12.25 10.10 12.25 10.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 44A REV. B
R
16
AT17F040/080
3039B-CNFG-10/02
AT17F040/080
44J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075)
E1 B
E
B1
D2/E2
e D1 D A A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 17.399 16.510 17.399 16.510 14.986 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 17.653 16.662 17.653 16.662 16.002 0.813 0.533 Note 2 Note 2 NOTE
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 44J REV. B
R
17
3039B-CNFG-10/02
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3039B-CNFG-10/02 xM

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